1. Field of the Invention
This invention relates to a memory type insulated gate field effect semiconductor device, and more particularly to a memory type insulated gate field effect semiconductor device which includes a semiconductor layer of one conductivity type, a source region of the opposite conductivity type formed in the surface of the semiconductor layer, a drain region of the opposite conductivity type formed in the surface of the semiconductor layer, a gate insulating layer affixed to the surface of the semiconductor layer, and a gate electrode deposited on the surface of the gate insulating layer, and in which the gate insulating layer has a pair of thick gate guarding portions existing on side of the source and drain regions, and a thin memory portion intermediate between the thick gate guarding portions.
2. Description of the Prior Art
In a conventional MNOS-type memory transistor, a gate insulating layer is so formed as to be thicker near source and drain regions than at a memory gate portion, in order to increase the brake-down voltages of the source and drain regions, and to guard the gate insulating layer against repeated writing pulses and erasing pulses. FIG. 1 shows the conventional MNOS-type memory transistor.
Referring to FIG. 1, N.sup.' -type source and drain regions 2 and 3 are formed in the surface of a P-type semiconductor substrate 1. A SiO.sub.2 layer 4 functioning as a gate insulating layer 5 is formed on the semiconductor substrate 1. The gate insulating layer 5 defines a pair of gate guarding portions 6 of thickness 400 to 1000A adjacent to the source and drain regions 2 and 3, and a memory portion 7 of thickness 20 to 30 A intermediate between the gate guarding portions 6. A Si.sub.3 N.sub.4 layer 8 of thickness 500 to 700A is formed on the SiO.sub.2 layer 4 and 5. A source electrode 9, a drain electrode 10 and a gate electrode 11 are deposited on the Si.sub.3 N.sub.4 layer.
In the memory transistor of FIG. 1, it is proved that the positive charge density of the thin memory portion 7 is higher than that of the thick gate guarding portions 6. Accordingly, in the enhancement type memory transistor, the threshold voltage V.sub.TH of the gate guarding portions 6 is higher than that of the memory portion 7, as shown in FIG. 2, When the semiconductor substract 1 is of the N-type conductivity and a P-type channel is formed therein, the V.sub.TH of the gate guarding portion 6 is lower than that of the memory portion 7, in negative polarity, as shown in FIG. 3.
The N-type channel memory transistor of FIG. 1 is equivalent to three MNOS-type memory transistors constituted by the memory portion 7 and the pair of the gate guarding portions 6 connected in series with each other. Accordingly, at the level "0", namely at the non-memorized state, the V.sub.TH of the memory transistor of FIG. 1 is that of the thick gate guarding portions 6. When a positive voltage is applied to the gate electrode 11 to inject electrons from the semiconductor substrate 1 into the boundary surface between the Si.sub.3 N.sub.4 layer 8 and the SiO.sub.2 layer 7, the memory transistor of FIG. 1 is put at the level "1", namely at the memorized state. The V.sub.TH of the memory portion 7 is raised up at the level "1", as shown in FIG. 4. Accordingly, the V.sub.TH of the memory transistor of FIG. 1 becomes that of the thin memory portion 7. There is a voltage difference (window of memory) between the V.sub.TH of the gate guarding portion 6 at the level " 0" and the V.sub.TH of the memory portion 7 at the level "1", in the memory transistor of FIG. 1.
Since it is preferable that the voltage difference between the V.sub.TH of the memory transistor at the level "0" and the V.sub.TH of the memory transistor at the level "1" is larger in consideration of attenuation of memory, a voltage difference between the V.sub.TH of the memory portion 7 at the level "0" and the V.sub.TH of the gate guarding portion 6 at the level "0" is undesirable. Accordingly, it is advantageous to make the V.sub.TH of the memory portion 7 approach to the V.sub.TH of the thick gate guarding portion 6 at the level "0".
In the P-type channel memory transistor, the V.sub.TH of the memory portion 7 at the level "0" is higher than that of the gate guarding portion 6 at the level "0", in negative polarity. Accordingly, there is no problem on the voltage difference between the V.sub.TH of the memory transistor at the level "0" and the V.sub.TH of the memory transistor at the level "1". However, since a read-out voltage needs to be about three times as high as the V.sub.TH of the memory transistor at the level "0", it is required that the read-out voltage is increased with the V.sub.TH of the memory transistor at the level "0", and that the voltage difference between the V.sub.TH of the memory transistor at the level "0" and the V.sub.TH of the memory transistor at the level "1" is increased with the read-out voltage. That affects the reliability of integrated circuits from the view point of memory attenuation. Accordingly, it is required to make the V.sub.TH of the memory portion 7 at the level "0" decrease or approach to the V.sub.TH of the gate guarding portion 6 at the level "1".